18/05/2023

*“The best SPS is its absence.” – not a good joke that the system engineers scare the battered and unhappy pulse converter developers with. ^{1}*

In the “first grade”, in the previous article, we considered the initial moments of construction of one of very important circuits for power electronics – a single-cyclel forward converter (FC). Two fundamental formulas were given – *for capacitance i* = *C du/dt and for inductance u = L di/dt.*

Four rules were formulated: that the capacitor voltage (#1) and the inductor coil current (#2) are constant over a small time interval, that the capacitor (#3) has zero ampere-second area per period, and that the inductor coil (#4) has zero volt-second area per period.

**Fig. 1** – Schematic diagram of the power section of a single-cycle forward converter

It is shown that for the simplest circuit of the forward converter (Fig. 1) *the transformer magnet wire is remagnetized along a symmetrical hysteresis loop using the maximum possible range of induction (!)*.

The output filter L_{1}, C_{1} of the forward converter is an excellent integrator, effectively isolating the average component of the output voltage in accordance with the regulation characteristic **U _{out} = @U_{in} N^{2}** without losses.

As a result, this *Mercedes* among other structures of DC/DC converters has a remarkable property – it even without any stabilizing feedback has a very small output resistance, i.e. in relation to the load has very useful properties of a voltage generator (with gapless choke currents).

So, the speed is picked up, let’s keep moving.

The real FC has voltage and current diagrams slightly different from those in the previous article.

**Fig. 2** – The diagrams of voltage and current of the power transistor FC drain

When transistor VT_{1} is turned off, a narrow spike, sometimes of significant magnitude, many times greater than the input voltage can be observed in the voltage diagram at the drain (Fig. 2a). The real presence of stored energy in the leakage inductance Ls of transformer T_{1}, **W = i ^{2}Ls/2**, causes a voltage overshoot at the drain of transistor VT

In fact, we are dealing with a double-circuit resonant system, in which the distributed and reduced capacitances of the transformer resonate separately and in combination with the inductances of Ls dissipation and L magnetization. The type of resulting voltages during the resonance processes can be different. Besides clear separation of “needle” and “navel”, one can observe “two-humped camel” and very often asymmetric voltage due to merged “needle” and “navel”, it is like half of a sinusoid with steep leading edge and flat trailing edge (the author hopes that readers will add exotic names of processes in forward converter). We should add that so far we are talking about the diagram shown in blue (Fig. 2a).

When transistor VT_{1} is turned on, a “horn” – a triangular current overshoot with a high-frequency transient – is observed on the current diagram (Fig. 2b). The appearance of this spike is due to the fact that at the moment of turning on of the transistor VT_{1} diode VD_{2} is still in the conducting state, the diode VD_{1} begins to open, resulting in a short circuit of the output winding of transformer T_{1}. In fact, transistor VT_{1} is switched to short-circuit transformer T_{1}, as a result of which a large extractor current flows through transistor VT_{1} for a short time – this terrible “horn” is born. By the way, its magnitude is limited by the dissipation inductance of transformer T_{1}, it is fortunately not short-circuited at this time.

For lovers of subtlety it should be added that there are other reasons for the inrush current when switching on, such as the discharge on the transistor VT_{1} of numerous previously charged capacitances, such as the capacitance of the transformer, etc.

How do forward converter transistors survive in such terrible conditions of existence, among “needles”, “horns” and “navels”?

First, only MOSFETs survive, with few exceptions. They have unique properties of speed, overload capability, and, most importantly, they have virtually no secondary breakdown phenomenon, which does not allow bipolar transistors to be used reliably in high-frequency forward converter.

Secondly, special circuit solutions are used to protect the transistors.

Circuit R_{1}, C_{3} briefly takes over the decreasing operating current of winding w_{1}, which allows quickly and elegantly (ie, without losses and overloads) turn off transistor VT_{1} with a relatively smooth rise in voltage at the drain. Slowing down the rate of change of current w_{1} at the turn-off stage of transistor VT_{1} reduces the amount of voltage overshoot at the drain – “needle”; *remember the formula for inductance*. Unfortunately, you have to pay for everything, here the payback is the additional load of the transistor VT_{1} at the on stage, because the charged capacitor C_{3} has to be discharged. The action of the circuit R_{1}, C_{3} professionals call “shaping the off-path” of transistor VT_{1}.

The dissipating inductance of transformer T_{1} can also be considered an element of the circuit, often its value in the forward converter, operating at high frequencies, increase the ferrite bead, dressed on the terminal of winding w_{1} of transformer T_{1}. The role of leakage inductance is twofold. On the one hand, it causes a voltage surge at the drain of the transistor VT_{1} “needle”, but on the other hand, it does not allow the extract current to develop through VT_{1} when it is turned on, limiting the “horn” of the current.

The “needle” is dealt with by means of various circuits, e.g. VD_{4}, C_{7}, R_{5} in Fig. 1. This circuit limits, trims the voltage overshoot, as shown by the red line in Fig. 2a.

Finally, the author cannot skip the circuit recommended in almost all textbooks consisting of an additional winding w_{3} and a diode VD_{3}. The diagram corresponding to the action of this circuit is highlighted in green.

The idea is simple. If in a DRC-chain such as VD_{4}, C_{7}, R_{5}, the power corresponding to the energy **W = i ^{2}Ls/2** stored in the dissipation inductance is uselessly dissipated as heat, then due to additional winding w

Unfortunately, it is difficult to implement this idea in a high-frequency converter and it is rarely used in practice. It is very difficult at high frequencies, more than 100 kHz, to ensure good magnetic coupling between windings w1 and w_{3}, for this it is necessary to wind these windings simultaneously. In this case there are difficulties with the breakdown voltage, so complex insulation has to be used. The w_{1} and w_{3} windings must have the same number of turns, and this is at odds with the desired variation range of @. And most importantly, introducing an extra winding into the transformer design results in increased Ls dissipation inductance, increased stored energy W, increased initial ejection pulse, etc., i.e., what was fought for…

Additional circuits, such as R_{4}, C_{6}; R_{2}, C_{4}; R_{3}, C_{5} shown in Fig. 1, are used to reduce the level of noise born in windings, circuit board elements, component pins, etc. due to sudden changes in voltages and currents.

At this point, it is useful for the tired reader to take a break, rest, drink tea, in general, gain strength to continue.

Let’s continue our consideration of the simplest forward converter with the question of voltage and current selection of transistors and diodes.

Let’s look at the diagrams shown in Fig. 2. With a maximum fill factor @, say 0.66, *in accordance with rule #4* (volt-second area equal to zero per period), it is easy to assume that the “navel”, if it is prescribed completely (which is the lowest navel height), will be about 1.4 times higher than the input voltage multiplied by 0.66 and divided by (1 – 0.66). Try to do these estimates geometrically. The formula is:

**U _{nav} = 1.4U_{in} _{min @}/(1 – @)**

Since U_{in min} is in effect at this time, the maximum voltage at the drain of transistor VT_{1} will be **U _{c max} = U_{in min} + U_{nav}**. Let’s take a typical range of input voltage variation multiple of

**U _{c max1} = 3.8U_{in max}/K = 1.9U_{in max}**

We can take @ = 0.33, which corresponds to U_{in max}. Here, of course, it is taken into account that we are considering a stabilized forward converter with a constant output voltage. Then, applying rule #4 (the umbilical height will remain the same), we get:

**U _{c max2} = U_{in max} + U_{nav} = 2,8_{Uin max}**

Of two evils we choose the worst – U_{c max2}.

Thus, if the “needle” – ejection due to the action of the leakage inductance – was not present, we would already have to choose transistor VT_{1} at triple the maximum supply voltage. But, unfortunately, the typical “needle” may well be 1.2…1.5 times higher than the “navel”. A voltage reserve of 20…30% wouldn’t hurt (K_{res} = 1.2…1.3).

The author recommends using the ratio for transistor selection by voltage in the simplest forward converter:

**U _{c max} = K_{res} (1,4 * 1,5U_{in max} + U_{in max}) = 4…5 U_{in max}**

The choice of transistor in terms of current for stabilized forward converter is made on the basis of output power of forward converter P_{out}, efficiency, input voltage U_{in} (the slope of the top of the current diagram is not considered).

Average current for the period **I _{c1} = P_{out} / (Efficiency × U_{in min}).** The pulse current is obtained by dividing this expression by @, corresponding to U

**I _{c max1} = (1.2…1.5) P_{out} K/(Efficiency * U_{in ma}x * @_{max})**

For U_{in max} we can get

**I _{c max2} = (1,2…1,5) P_{out}/(Efficiency * U_{in max} * @_{min})**,

of course in this case

**@ = @ _{min} = @_{max}/K = 0,33**

Thus, **I _{c max1}** = I

The author recommends using the ratio to select transistor VT_{1} by current in the simplest forward converter (typical efficiency = 0.8, and the top bevel must be taken into account, ~1.2):

I_{c max} = 1,5 × 1,2 K_{res} P_{out} K/(Efficiency * U_{in max} * @_{max}) =** 8…10 P _{out}/U_{in max}**

The esteemed reader understands that one can put up with such a choice of current, given the large current overload capacity of MOSFETs; after all, this is power, due to the pulse principle of operation. But it is not always possible to put up with a very high drain voltage excess ratio in a MOSFET. Imagine that the maximum input voltage is 360 V! (Rectified voltage at the upper limit is ~220 V.) Then MOSFETs with a maximum drain voltage of 1400…1800 V must be used (and there are virtually none!).

By means of noticeable efficiency loss (from 80% to 75…70%) it is possible to cut not only “needle” but also a part of “navel” itself in the simplest PSC. Then maybe **U _{c max} = 2…3 U_{in max}**, although this is also a lot.

Science suggests two solutions here, aimed at reducing overvoltage and increasing efficiency.

The first solution, the so-called “active limitation” means removal of active resistance in the DRC-chain VD_{4}, C_{7}, R_{5}, shown in Fig. 1, and allowing current to flow against diode VD_{4} in pause (with a small dead time to eliminate through currents) – Fig. 3.

**Fig. 3** – A forward converter scheme with active surge limitations

For such a forward converter, a capacitor C_{7} with a capacitance large enough to make the accumulated voltage of emissions on it more or less constant is chosen.

**Fig. 4** – Voltage and current diagrams in the forward converter circuit with active limiting

The auxiliary transistor VT_{2} is switched on with a small delay after switching off VT_{1} (Fig. 4) and is switched off a little before the main transistor VT_{1} is switched on. All of the voltage rise energy at the drain of transistor VT_{1} passes into the energy of capacitor C_{7}, **W = C * U _{c2}/2**, as current flows through the circuit – open VD

After switching off the additional transistor VT_{2} the current developed by this moment in the winding w_{1} and, therefore, led to the accumulation of energy in the leakage inductance Ls of transformer T_{1}, **W = i ^{2}Ls/2**, is now shorted to the reduced capacity of the primary winding w

The most important thing happens – the overvoltage at the drain of the power transistor (Fig. 4a) decreases sharply. In such a circuit, efficiency losses are small, and the power transistor VT_{1} is turned on more gently, with less noise – the “horn” of the drain current is reduced.

Another circuit solution is called an “oblique half-bridge”. You can see why it is an oblique bridge from Fig. 5.

**Fig. 5** – Forward converter scheme – oblique half-bridge

In this circuit, the energy of the voltage spikes is recovered into the primary power supply using diodes VD_{3}. This keeps the efficiency high.

But most importantly, this circuit allows the lowest voltage at the drain of power transistors VT_{1}. It does not exceed the supply voltage U_{in}.

Of course, the esteemed reader understands that the power transistors open and close simultaneously.

The oblique half-bridge circuit is widely used in forward converter designed to operate with higher input supply voltages. This remarkable circuit allows the use of relatively cheap power transistors with a low breakdown voltage. In this case one of its disadvantages – sequential inclusion of two transistors in the path of the operating current of transformer T_{1} winding w_{1} – is smoothed by the fact that low-voltage transistors have a reduced open channel resistance, so that large power losses do not occur.

The voltage and current diagrams for the oblique half-bridge circuit are shown in Fig. 6.

**Fig.** 6 – Voltage and current diagrams in an oblique half-bridge circuit

*The author has cheated a bit here by not giving voltage diagrams for the transistors. Consideration of the voltage on the winding w _{1} of transformer T_{1} is suggested because the voltage diagrams on power transistors VT_{1} may have a different, sometimes bizarre appearance, depending on the symmetry (similarity) of transistors VT_{1} not only in static, but also in dynamics.*

^{1}Author’s Explanation:

1) SPS is a Secondary Power Supply;

2) battered and unhappy – because the system engineers sometimes beat them, because they are sure that the crucial problem in their system is a SPS, even if microprocessors do not count and motors do not spin, the bad one is a SPS;

3) in truth, the author is sure that the SPS was called secondary by evil system designers due to the fact that they always don’t have time to give out input data for power supply design in a timely manner and by that point all convenient design volumes of hardware have already been distributed among their (primary, important) devices;

4) according to importance of consequences for system in case of failure of SPS it is long ago time to rename it to Primary, and qualification of developers of SPS is required very high, here cannot work craftsmen, there should be masters – poets…